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Reports (Research Report) Year : 2006

Synchronous Modeling of Data Intensive Applications

Abstract

In this report, we present the first results of a study on the modeling of data-intensive parallel applications following the synchronous approach. More precisely, we consider the Gaspard extension of Array-OL, which is dedicated to System-on-Chip codesign. We define an associated synchronous dataflow equational model that enables to address several design correctness issues (e.g. verification of frequency / latency constraints) using the formal tools and techniques provided by the synchronous technology. We particularly illustrate a synchronizability analysis using affine clock systems. Directions are drawn from these bases towards modeling hierarchical applications, and adding control automata involving verification.
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Dates and versions

inria-00001216 , version 1 (06-04-2006)

Identifiers

  • HAL Id : inria-00001216 , version 1

Cite

Abdoulaye Gamatié, Eric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser. Synchronous Modeling of Data Intensive Applications. [Research Report] RR-5876, INRIA. 2006, pp.21. ⟨inria-00001216⟩
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