Communication Dans Un Congrès Année : 2025

Polysilicon PIN diode characterization and scaling in low-cost 40nm technology for IoT applications

Résumé

The integration of PN diodes on bulk silicon technologies often leads to shot noise and significant parasitic effects such as latch-up which arises when a parasitic transistor is unintentionally triggered, leading to undesired current flows. To address these issues, and enable operation in higher voltage ranges, this work investigates the use of unexplored polysilicon PIN diodes implemented on an insulating area as an alternative solution to PN diodes integrated on bulk substrates. The geometric design and process optimizations of the PIN diode structure are explored to optimize its performances (forward and leakage currents, series resistance, threshold, and breakdown voltages) while ensuring compatibility with low-cost analog circuits fabricated in an 40nm technology dedicated to IoT applications. Compared to classical PN diodes, PIN diodes require a simple fabrication process and can provide a breakdown voltage twice higher. However, this improvement comes at the expense of an increased leakage current and series resistance.

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hal-05574083 , version 1 (31-03-2026)

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Wiame El Khayyari, Noemie Couzi, Jeremy Postel-Pellerin, Hassen Aziza, Abderrezak Marzaki, et al.. Polysilicon PIN diode characterization and scaling in low-cost 40nm technology for IoT applications. 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS 2025), Nov 2025, Marrakech, Morocco. ⟨10.1109/ICECS66544.2025.11270704⟩. ⟨hal-05574083⟩
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