In-Depth 2D FEM Analysis of Gate Cracking in SiC MOSFETs Under Repetitive Short-Circuit Conditions: Application of the Rankine Model for Crack Length Prediction
Résumé
An advanced structural and physical model of Intermediate-Layer-Dielectric (ILD) cracking in a planar gate under short-pulse short-circuit conditions has been developed as a continuation of our previous studies. This approach utilizes an energy-based Rankine damage model, which is applied based on the mechanical properties of SiO2. The Rankine model has been seamlessly integrated into a comprehensive 2D electrothermal-metallurgical and elastoplastic-mechanical framework, which accounts for both the high-temperature rise and its return to its reference value. In a novel approach, multiple repetitive mechanical cycles were simulated to evaluate the progression and rate of crack penetration, with variations in parameters such as pulse duration and damage model coefficients. This model illustrated the evolution of crack formation and direction during cycling, in alignment with the crack progression observed experimentally in microsections.
| Origine | Fichiers produits par l'(les) auteur(s) |
|---|---|
| Licence |