Communication Dans Un Congrès Année : 2025

Ahead of Time Generation for GPSA Protection in RISC-V Embedded Cores

Résumé

State-of-the-art hardware countermeasures against fault attacks are based, among others, on control-flow and code integrity checking. Generalized Path Signature Analysis and Continuous Signature Monitoring can assert these integrity properties. However, many implementations of such mechanisms require a dedicated compiler flow and do not support indirect jumps, while others have prohibitive overheads. This work proposes a technique based on a ahead-of-time analysis to generate those signatures, associated with a hardware/software runtime handling indirect jumps while executing unmodified off-the-shelf RISC-V binaries. The proposed approach has been implemented on a pipelined processor, and experimental results show an average slowdown of ×1.82 and an area overhead of at least ×1.3 compared to unprotected implementations.

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Dates et versions

hal-05100014 , version 1 (05-06-2025)
hal-05100014 , version 2 (25-08-2025)

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  • HAL Id : hal-05100014 , version 1

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Louis Savary, Simon Rokicki, Steven Derrien. Ahead of Time Generation for GPSA Protection in RISC-V Embedded Cores. ASAP 2025 - 36th IEEE International Conference on Application-specific Systems, Architectures and Processors, Jul 2025, Vancouver (BC), Canada. pp.65-72. ⟨hal-05100014v1⟩
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