Communication Dans Un Congrès Année : 2025

13.5 An 18.5µW/qubit cryo-CMOS charge-readout IC demonstrating QAM multiplexing for spin qubits

Résumé

Spin qubits are a promising candidate for large-scale fault-tolerant quantum computing due to <1µm2 footprint per qubit, higher operating temperature (up to 1K [1]) and possible compatibility with industrial CMOS processes [2], [3]. However, the need for a simultaneous ~µs readout of thousands of devices is especially challenging in terms of power consumption and footprint per qubit [4], [5]. Frequency-domain multiplexed (FDM) reflectometry architectures using cryo-CMOS have been introduced in [6], [7], [8] but these circuits require bulky > 100µm2 inductors and do not match readout time specifications using actual quantum devices. Besides, current integrator readout schemes have been proposed [9], [10], but offer no scaling perspectives beyond time-domain multiplexing, leading to strong constraints in terms of bandwidth and power consumption. Recently, [4] introduced a capacitive-feedback transimpedance amplifier achieving an inductor-less FDM readout of two quantum dots [11]. Nevertheless, the demonstrated power consumption per qubit of 214µW/qubit remains too high to match the maximum heat dissipation allowed near quantum devices [12] in a large-scale perspective. Moreover, the used On-Off Keying (OOK) modulations are limited to one qubit per carrier, thus requiring high bandwidth and power consumption in order to read thousands of qubits.

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hal-04981624 , version 1 (07-03-2025)

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Quentin Schmidt, Baptiste Jadot, Brian Martinez, Antoine Faurie, Tristan Meunier, et al.. 13.5 An 18.5µW/qubit cryo-CMOS charge-readout IC demonstrating QAM multiplexing for spin qubits. ISSCC 2025 - 2025 IEEE International Solid-State Circuits Conference, IEEE, Feb 2025, San Francisco, United States. pp.244-246, ⟨10.1109/ISSCC49661.2025.10904808⟩. ⟨hal-04981624⟩
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