Communication Dans Un Congrès Année : 2025

A 860mV and 73.5Ppm/°C Voltage Reference that Relies on Back-Gate Biasing Techniques in 28nm FD-SOI Technology

Résumé

This paper discusses the development of a new topology voltage reference in Fully Depleted Silicon-On-Insulator (FD-SOI) technology. The voltage reference described in this paper is based on threshold voltage subtraction techniques, PTAT and CTAT voltage addition and transistor's back-gate biasing in 28nm FD-SOI technology. It has a 860mV output and achieves a performance of 73.5ppm/°C (T=-50°C to 150°C) under a supply voltage of 1V.

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Dates et versions

hal-04945900 , version 1 (13-02-2025)

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Maxime Guillot, Yann Deval, Herve Lapuyade, François Rivet. A 860mV and 73.5Ppm/°C Voltage Reference that Relies on Back-Gate Biasing Techniques in 28nm FD-SOI Technology. 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2024, Nancy, France. pp.1-4, ⟨10.1109/icecs61496.2024.10849174⟩. ⟨hal-04945900⟩
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