A 860mV and 73.5Ppm/°C Voltage Reference that Relies on Back-Gate Biasing Techniques in 28nm FD-SOI Technology
Résumé
This paper discusses the development of a new topology voltage reference in Fully Depleted Silicon-On-Insulator (FD-SOI) technology. The voltage reference described in this paper is based on threshold voltage subtraction techniques, PTAT and CTAT voltage addition and transistor's back-gate biasing in 28nm FD-SOI technology. It has a 860mV output and achieves a performance of 73.5ppm/°C (T=-50°C to 150°C) under a supply voltage of 1V.