n the frame of the development of next generation low cost power devices, Gallium nitride (GaN) grown on Silicon (Si) is an undeniable technology that combines the high physical properties of GaN (large band gap, high electron mobility and high electric field) and the cost-effective Si fabrication technology. Lateral GaN-based high electron mobility transistors (HEMTs) on Si substrate are thus a promising candidate with proven high performances. However, several drawbacks slow down the industrialization of this technology for high voltage applications (> 650 V) such as a destructive breakdown voltage (BV), a complex epitaxy and large device size [1]. To overcome this limitation, the junction based vertical GaN-on-Silicon technology could be an attractive alternative. Indeed, the vertical structure allows a better electric field management potentially resulting in low charge trapping issues. Moreover, the BV occurs due to impact ionization, which results in a non-destructive breakdown and thus unlock the avalanche capability. Finally, owing to the vertical transport, the device size can be smaller compared to high voltage lateral architectures. Recently, pseudo vertical (PV) GaN-on-Si pn diodes have been developed with few attempts of fully vertical devices [2]. However, high current spreading in large devices has not been yet demonstrated, although this is a key requirement for power electronics. Current crowding effect in the case of pseudovertical devices is a major issue that prevents the achievement of large current (i.e. large device dimension with low onresistance). Therefore, the development of a robust fully vertical (FV) structure with high processing and growth quality is critical to unveil the potential of this technology.