A Performant Quantum-Resistant KEM for Constrained Hardware: Optimized HQC
Abstract
Secure Key Encapsulation Mechanisms (KEMs) are necessary for providing authentication and confidentiality
through symmetrical encryption. The emergence of quantum computers is a threat to current KEM standards,
therefore new quantum-resistant algorithms have been developed in recent years. One of these propositions
is the code-based Hamming Quasi-Cyclic (HQC) algorithm. However, a lightweight version of this algorithm
is required to run on low-performance systems such as Internet of Things (IoT) devices or small Unmanned
Aerial Vehicles (UAVs). This article presents an algorithmic optimization of the HQC algorithm applied on
constrained hardware. The goal is to improve the performance for real-life applications, and thus the test
bed uses a Real-Time Operating System (RTOS) to emulate a system able to complete complex tasks. This
optimization reduces the completion time of key generation, encapsulation, and decapsulation by a factor of 10,
and reduces significantly the Random Access Memory (RAM) usage for the algorithm. These improvements
make HQC viable for real-life applications on constrained hardware, and the performance could be further
improved by using hardware-specific optimizations.
Domains
Engineering Sciences [physics]Origin | Files produced by the author(s) |
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