Is RISC-V ready for Space? A Security Perspective - Archive ouverte HAL
Communication Dans Un Congrès Année : 2022

Is RISC-V ready for Space? A Security Perspective

Résumé

Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and viable w.r.t. performance. On the other hand, this design paradigm exposes the system to a number of security threats both at design-time and at runtime. In this paper, we discuss the security issues related to space applications mainly focusing on threats that come from the adoption of the well-known RISC-V microprocessor. We highlight how Hardware Trojan horses (HTHs) and Microarchitectural Side-Channel Attacks (MSCAs) may compromise the overall system operation by either altering its nominal behavior or by stealing secret information. We discuss the security extensions provided by the RISC-V architecture as well as their limitations. The paper is concluded by an overview of the issues that are still open regarding the security of such microprocessor in the space domain.
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Dates et versions

hal-04685569 , version 1 (03-09-2024)

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Luca Cassano, Stefano Di Mascio, Alessandro Palumbo, Alessandra Menicucci, Gianluca Furano, et al.. Is RISC-V ready for Space? A Security Perspective. 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2022, Austin, United States. ⟨10.1109/dft56152.2022.9962352⟩. ⟨hal-04685569⟩
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