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Communication Dans Un Congrès Année : 2024

Design of Low-Power 5 . 8-GHz ULV LNTAs using Normalized Biasing Metric

Résumé

This paper explores computational methodologies for transistor sizing for ultra-low power (ULP) complemen- tary metal-oxide-semiconductor (CMOS) design. The proposed approach uses normalized biasing metric to minimize power consumption while maintaining performance integrity under ultra-low voltage (ULV). The effectiveness of these metrics in streamlining the design process and improving device reliabil- ity is demonstrated through low-noise transconductance ampli- fier (LNTA) inverter-based design and comparative analyses. The optimized LNTA design in a 65 nm CMOS process operates at 5.8 GHz, achieving a noise figure (NF) from 2.5 to 3.8 dB and a gain between 10.02 to 14.98 dB, while consuming power from 43.07 µW to 207.40 µW, and an input third-order intercept point (IIP3) from -14.38 to -9.06 dBm. The design LNTA versions presented the best figure of merit (FoM) in comparison to other works from the literature.
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Dates et versions

hal-04631371 , version 1 (02-07-2024)

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Copyright (Tous droits réservés)

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  • HAL Id : hal-04631371 , version 1

Citer

Vanessa M. da F. Botinelly, Filipe F. Caetano, Pietro M. Ferreira, Osamu Saotome, Lucas Compassi-Severo. Design of Low-Power 5 . 8-GHz ULV LNTAs using Normalized Biasing Metric. 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design (SBCCI), Sep 2024, João Pessoa (PB), Brazil. ⟨hal-04631371⟩
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