This paper explores computational methodologies for transistor sizing for ultra-low power (ULP) complemen- tary metal-oxide-semiconductor (CMOS) design. The proposed approach uses normalized biasing metric to minimize power consumption while maintaining performance integrity under ultra-low voltage (ULV). The effectiveness of these metrics in streamlining the design process and improving device reliabil- ity is demonstrated through low-noise transconductance ampli- fier (LNTA) inverter-based design and comparative analyses. The optimized LNTA design in a 65 nm CMOS process operates at 5.8 GHz, achieving a noise figure (NF) from 2.5 to 3.8 dB and a gain between 10.02 to 14.98 dB, while consuming power from 43.07 µW to 207.40 µW, and an input third-order intercept point (IIP3) from -14.38 to -9.06 dBm. The design LNTA versions presented the best figure of merit (FoM) in comparison to other works from the literature.