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Article Dans Une Revue Photonics Année : 2024

STI patterning to improve FSI PDP of SPAD integrated in FD-SOI CMOS technology

Résumé

The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated layer created by an optimized arrangement of Shallow Trench Isolation (STI) above the photosensitive zone generates constructive interferences and consequently an increase in the light sensitivity in the frontside illumination. A simulation methodology is presented that couples electrical and optical data in order to optimize the STI trenches (size and period) and to estimate the Photon Detection Probability (PDP) gain. Then, a test chip was designed, manufactured, and characterized, demonstrating the PDP improvement due to the STI nanostructuring while maintaining a comparable Dark Count Rate (DCR)
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hal-04599693 , version 1 (04-06-2024)

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Shaochen Gao, Vu Duc-Tung, Thibauld Cazimajou, Patrick Pittet, Martine Le Berre, et al.. STI patterning to improve FSI PDP of SPAD integrated in FD-SOI CMOS technology. Photonics, 2024, 11 (6), pp.526. ⟨10.3390/photonics11060526⟩. ⟨hal-04599693⟩
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