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Journal Articles IEEE Access Year : 2024

Novel digital NGD Methodology for FPGA-based Embedded Systems

Abstract

Negative Group Delay (NGD) is a concept not widely explored in embedded digital signal processing systems, and this study aims to fill this gap. It presents a novel methodology for implementing NGD using second-order Finite Impulse Response (FIR) filter. We include synthesis results that prove the viability of using FIR filters for NGD functions under specific conditions, which involve considering asymmetry coefficients in the time domain. The synthesized results demonstrate the desired time-advance values relative to the input signal frequency, and it is observed that as the normalized advanced-time increases, the normalized frequency also increases. We then design, simulate and test FIR-based NGD parameters before building an FPGA-based proof-of-concept implementation for embedded systems. The experimental results show how the frequency responses of the NGD function at baseband frequency correlate well with the theoretical hypothesis, supporting our analysis and validating our methodology. NGD time-domain characterization was conducted using a sampling frequency of 1 MHz and Gaussian and sinc input signal waveforms. The calculated and experimental results are in excellent agreement, showing a desired time advance of 6 μ s and an average cross-correlation of 98%. The NGD principle presented in this paper is potentially useful for group delay correction processes and signal pure delay reduction in embedded digital signal processing systems.

Dates and versions

hal-04596488 , version 1 (31-05-2024)

Identifiers

Cite

Rivo Randriatsiferana, Jordane Lorandel, Ruben Salvador, Christophe Moy. Novel digital NGD Methodology for FPGA-based Embedded Systems. IEEE Access, 2024, ⟨10.1109/access.2024.3403033⟩. ⟨hal-04596488⟩
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