Flexible design methodology for spike encoding implementation on FPGA - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2022

Flexible design methodology for spike encoding implementation on FPGA

Résumé

Spiking Neural Networks (SNNs) are promising candidates for low power and low latency embedded artificial intelligence, e.g., for edge computing. There is, however, a lack of naturally event-based sensors that could directly feed those networks, except for a few specialized flagship examples like neuromorphic retinas. Using conventional sensors in conjunction with SNNs requires to encode their outputs into spikes, which can be detrimental to energy consumption or latency when performed in software. Spike-encoding algorithms have been studied within specific contexts in the literature but are often limited to a software implementation. Here we introduce a flexible design methodology for implementing a generalized version of such a spike-encoder on Field Programmable Gate Array (FPGA). Our approach relies on High-Level Synthesis, which allows to quickly evaluate different hardware architectures to tailor the solution to the application needs. This work could accelerate the development of lower power and lower latency smart sensors by combining conventional, possibly off-the-shelf, sensors with hardware SNNs.
Fichier non déposé

Dates et versions

hal-04570859 , version 1 (07-05-2024)

Identifiants

Citer

Clemence Gillet, Adrien F. Vincent, Bertrand Le Gal, Sylvain Saïghi. Flexible design methodology for spike encoding implementation on FPGA. 2022 IEEE Biomedical Circuits and Systems Conference (BioCAS), Oct 2022, Taipei, Taiwan. pp.379-383, ⟨10.1109/BioCAS54905.2022.9948601⟩. ⟨hal-04570859⟩
13 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Mastodon Facebook X LinkedIn More