MRAM-on-FDSOI Integration: A Bit-Cell Perspective - Archive ouverte HAL
Communication Dans Un Congrès Année : 2018

MRAM-on-FDSOI Integration: A Bit-Cell Perspective

Résumé

In this paper we discuss the potential foundry announced hybrid integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FD-SOI) technology. The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next generation voltage-controlled magnetic anisotropy (VCMA) MTJ are separately integrated into a 28 nm FD-SOI process. Circuit-level design strategies are explored that use FD-SOI leverage and spin-device characteristic to realize writing and reading power-delay efficiency, robust and reliable performance in a 1-transistor 1-MTJ (1T1M) bit cell. Process variation aware strategies for MTJ-FDSOI integration are proposed to compensate failure operations, by using the dynamic step-wise back-bias and the flip-well back-bias. A qualitative summary demonstrates that the MRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration.
Fichier non déposé

Dates et versions

hal-04477718 , version 1 (26-02-2024)

Identifiants

Citer

Hao Cai, You Wang, Wang Kang, Lirida Naviner, Xinning Liu, et al.. MRAM-on-FDSOI Integration: A Bit-Cell Perspective. 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul 2018, Hong Kong, China. pp.263-268, ⟨10.1109/ISVLSI.2018.00056⟩. ⟨hal-04477718⟩
25 Consultations
0 Téléchargements

Altmetric

Partager

More