In this paper we discuss the potential foundry announced hybrid integration of magnetic random access memory (MRAM) on fully depleted silicon-on-insulator (FD-SOI) technology. The spin transfer torque magnetic tunnel junction (STT-MTJ) and the next generation voltage-controlled magnetic anisotropy (VCMA) MTJ are separately integrated into a 28 nm FD-SOI process. Circuit-level design strategies are explored that use FD-SOI leverage and spin-device characteristic to realize writing and reading power-delay efficiency, robust and reliable performance in a 1-transistor 1-MTJ (1T1M) bit cell. Process variation aware strategies for MTJ-FDSOI integration are proposed to compensate failure operations, by using the dynamic step-wise back-bias and the flip-well back-bias. A qualitative summary demonstrates that the MRAM-on-FDSOI integration offers attractive performance for future non-volatile CMOS integration.