Approximate computing is a new design paradigm in VLSI design and test. It can improve the performance of error-tolerant applications at the expense of slight loss in computational accuracy. In this paper, we propose a novel approximate adder with a hybrid structure (HYB-adder) which produces results of different precision. The proposed adder is synthesized by utilizing 28nm FD-SOI (fully-depleted silicon-on-insulator) technology. The proposed HYB-adder outperforms existing approximate adder designs regarding mean error distance with comparable area, delay and power consumption. The efficiency is also validated by its application in DCT/IDCT procedures.