Voltage-controlled (VC) magnetic random access memory (MRAM) is considered as an alternative magnetic free layer switching mechanism, owing to its reduced bit-cell size and writing energy consumption comparing to spin-transfer-torque (STT)-MRAM. Unlike current driven mechanisms, voltage pulse is applied to modulate the magnetic anisotropy of magnetic tunnel junction (MTJ), so the write operation of VC-MTJ is sensitive to pulse shape. This paper investigates the reliability-aware VC-MTJ switching in the 1T-1M bit cell structure and write failures mainly caused by the pulse shape uncertainties and amplitude fluctuations. We propose a write-after-read scheme combined with a reverse bias at array bit-line (BL) to alleviate the MTJ unsuccessful switching, which achieves 52%-68.7% failure rate reduction in parallel/antiparallel state change of MTJ free layer. The design trade-off exists as additional control units, 1.71× writing latency, as well as 3.27× energy consumption realized with a 28nm CMOS process.