Ultra-low Power Access Strategy for Process-Voltage-Temperature Aware STT-MRAM - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2021

Ultra-low Power Access Strategy for Process-Voltage-Temperature Aware STT-MRAM

Résumé

With the development of circuit integration, low power consumption design has become the design challenge of on-chip memory. This work focuses on ultra-low power access strategy for STT-MRAM. A high margin voltage sensing amplifier (VSA) is implemented based on the bit-line (BL) parasitic capacitance, whereas a pulse-detect write self-termination is included for MRAM writing. Simulation is performed based on 28-nm CMOS and 40-nm CD magnetic tunnel junction (MTJ). Monte Carlo simulation show that the proposed sensing circuit achieves a reading yield of over 98% as well as 38% energy saving compared to previous work. Meanwhile, the self-termination scheme achieves an energy saving for more than 80%. These MRAM access strategies is well-adapted to process-voltage-temperature (PVT) variations including Tunnel Magneto Resistance (TMR) (20%-200%), temperature (0℃-120℃) and supply voltage (0.6V-1.8V).
Fichier non déposé

Dates et versions

hal-04477660 , version 1 (26-02-2024)

Identifiants

Citer

You-You Zhang, Lirida Naviner, Hao Cai. Ultra-low Power Access Strategy for Process-Voltage-Temperature Aware STT-MRAM. 2021 IEEE 14th International Conference on ASIC (ASICON), Oct 2021, Kunming, China. pp.1-4, ⟨10.1109/ASICON52560.2021.9620529⟩. ⟨hal-04477660⟩
8 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Mastodon Facebook X LinkedIn More