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Communication Dans Un Congrès Année : 2023

Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors

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Embedded systems in critical domains require both hard real-time and reliable execution. Real-time execution requires bounds in the worst-case execution time, while reliable execution is under threat, as systems are becoming more and more sensitive to transient faults. Thus, systems should be enhanced with fault-tolerant mechanisms with bounded error detection and correction overhead. Such mechanisms are typically based on redundancy at different granularity levels. Coarse-grained granularity has low comparison overhead, but may jeopardize timing guarantees. Fine-grained granularity immediately detects and corrects the error, but its implementation has increased design complexity. To mitigate this design complexity, we leverage high-level specification languages to design intrusive fine-grained lockstep processors based on the use of shadow registers and rollback, with bounded error detection and correction time, being appropriate for critical systems.
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hal-04397673 , version 1 (16-01-2024)

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Pegdwende Romaric Nikiema, Angeliki Kritikakou, Marcello Traiola, Olivier Sentieys, Olivier Sentieys. Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors. DSN 2023 - 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, Jun 2023, Porto, Portugal. pp.224-229, ⟨10.1109/DSN-S58398.2023.00062⟩. ⟨hal-04397673⟩
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