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Communication Dans Un Congrès Année : 2022

FPGA accelerators HLS-based design of hyper complex LMS filters

Résumé

In this paper, it is explored the use of the high- level synthesis (HLS) tool to design field-programmable gate array (FPGA)-based Quaternion Least Mean Square (QLMS) filters. The QLMS behaviour is modelled in system level C-code, and performance criteria, such as parallelism level and timing closure requirements, set through specific directives. The design outcome is a synthesizable hardware description model of the QLMS filter, and its implementation performance is evaluated for different data type representations. The results demonstrate that HLS is a framework that allows rapid design development and efficient FPGA implementation and opens the hyper complex filters hardware design to a larger design community.

Domaines

Electronique
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Dates et versions

hal-04364843 , version 1 (27-12-2023)

Identifiants

Citer

Alin Tisan, Eric Monmasson, Clive Cheong Took. FPGA accelerators HLS-based design of hyper complex LMS filters. IECON 2022 – 48th Annual Conference of the IEEE Industrial Electronics Society, Oct 2022, Brussels, Belgium. pp.1-6, ⟨10.1109/IECON49645.2022.9968783⟩. ⟨hal-04364843⟩
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