Backside Fault Localization and Defect Physical Analysis of Degraded Power HEMT p-GaN Transistors Stressed in DC and AC Switching Modes - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2023

Backside Fault Localization and Defect Physical Analysis of Degraded Power HEMT p-GaN Transistors Stressed in DC and AC Switching Modes

Résumé

Abstract This paper describes a backside approach methodology for sample preparation, fault localization and physical defect analysis on p-GaN power HEMT electrically stressed in DC voltage surge and AC switching mode. The paper will show that preparation must be adapted according to the defect position (metallurgy, dielectric layers, epitaxy, etc.) which depends on the type of stress applied. In our life-operation mode amplified electrical stress reliability study, the failure analysis will help us to reveal the weakest parts of the transistor design in relation to the type of applied stress. The failure analysis presented in this paper is composed of electrical characterization, defect localization with PEM and LIT, FIB Slice&View, TEM analysis and frontside conductive AFM after a deep HF.
Fichier principal
Vignette du fichier
Full_paper_ISTFA23_FV4-HAL.pdf (1.71 Mo) Télécharger le fichier
Origine : Fichiers produits par l'(les) auteur(s)

Dates et versions

hal-04307540 , version 1 (26-11-2023)

Identifiants

Citer

L. Ghizzo, G. Guibaud, C. de Nardi, F. Jamin, V. Chazal, et al.. Backside Fault Localization and Defect Physical Analysis of Degraded Power HEMT p-GaN Transistors Stressed in DC and AC Switching Modes. 49th International Symposium for Testing and Failure Analysis ISTFA 2023), Nov 2023, Phoenix, United States. pp.491-499, ⟨10.31399/asm.cp.istfa2023p0491⟩. ⟨hal-04307540⟩
91 Consultations
30 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More