Hybrid Hardening Approach for a Fault-Tolerant RISC-V System-on-Chip
Résumé
We propose fault tolerance strategies applied to a soft-core RISC-V-based System-on-Chip. Notably, we investigate the effectiveness of a multilayer hardening strategy, which combines software recoverability and hardware redundancy. As validation, a neutron irradiation campaign was performed.
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2023___RADECS___Hybrid_Hardening_Approach_for_a_Fault_Tolerant_RISC_V_System_on_Chip.pdf (81.21 Ko)
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