This article analyses the introduction of airgaps in the interconnect network of SOI-CMOS based RF switches to significantly reduce the off-state capacitance COFF without degrading the on-state resistance RON. Based on the 130 nm node of an existing RF-SOI-CMOS technology, an accurate COFF evaluation is performed by calculating the respective contributions of the interconnects and the intrinsic transistor separately. The impact of the relative airgap volume is simulated and results in an ultimate COFF reduction of 24.6% when the intermetal dielectric is completely replaced by air. It is shown that most of the reduction in COFF is achieved by introducing airgap at the first metal level. The airgap approach is verified experimentally by partially eliminating the interconnect dielectric of RF switches in post-process etching steps. A measured COFF improvement of 21.7 fF/mm (7.2%) and 18.3 fF/mm (6.3%) is demonstrated for 0.14 and 0.16 µm gate length transistors for which the airgap volume is only partial.