A gem5-based CVA6 Framework for Microarchitectural Pathfinding
Résumé
Succesfully designing a well-balanced general purpose processor targeting an ASIC implementation is an arduous task. As a result, software timing models are generally developped to enable fast design space exploration in the pathfinding phase. Those models are later tightly correlated to RTL as it becomes available, but can still provide valuable insight late in the design phase as they can simulate large workloads and provide non-intrusive access to internal information. In this paper, we leverage the gem5 timing simulator infrastructure to provide a fast timing simulation environment to drive microarchitectural improvements for the risc-v CVA6 processor. We also depict a correlation flow to ensure that the timing performance model keeps projecting meaningful performance numbers.