Memory Window in Si:HfO 2 FeRAM arrays: Performance Improvement and Extrapolation at Advanced Nodes
Résumé
The Memory Window (MW) of BEOL-integrated Si:HfO 2-based 16kbit 1T1C FeRAM arrays is shown to be significantly improved (×3) by etching the ferroelectric (FE) film of the Ferroelectric CAPacitor (FeCAP). To estimate the MW evolution in larger arrays at advanced technology nodes, a Preisach current-based compact model is developed, calibrated on measured FeCAP electrical characteristics and validated at various operating voltages. Electrical simulations of an elementary 1T1C 16kbit FeRAM array-like structure using Siemens Eldo show that scaling the transistor (1T) at advanced technology nodes can be beneficial for the MW. FE film thickness reduction below 10nm will also be requested for low voltage applications.
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