Arithmetic for Crypto in FPGA: HDL or HLS? - Archive ouverte HAL Access content directly
Conference Papers Year :

Arithmetic for Crypto in FPGA: HDL or HLS?


When implementing arithmetic for cryptographic circuits, choosing an appropriate design method among HDL and HLS is key for short research projects. Hardware description languages (HDL), such as VHDL or Verilog, and related synthesis tools allow to master low level details but require important efforts. High-level synthesis (HLS) uses "higher" level languages, such as C, and specific tools to quickly produce circuits but with a much reduced control in implementation details. Only very basic arithmetic support is available in HDL and HLS. Based on research work done in recent years, we will illustrate some of their pros and cons.
wrac23.pdf (1.54 Mo) Télécharger le fichier
Origin : Files produced by the author(s)
Licence : CC BY NC ND - Attribution - NonCommercial - NoDerivatives

Dates and versions

hal-04126074 , version 1 (13-06-2023)


Attribution - NonCommercial - NoDerivatives


  • HAL Id : hal-04126074 , version 1


Arnaud Tisserand. Arithmetic for Crypto in FPGA: HDL or HLS?. WRACH : Workshop on Randomness and Arithmetics for Cryptographic Hardware, Jun 2023, Roscoff, France. ⟨hal-04126074⟩
20 View
2 Download


Gmail Facebook Twitter LinkedIn More