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Communication Dans Un Congrès Année : 2023

Formal Verification of Divider Circuits by Hardware Reduction

Résumé

The paper introduces a novel verification method of gate-level hardware implementation of divider circuits. The method, called hardware reduction, accomplishes the verification by appending the divider circuit with another circuit, which implements its arithmetic inverse, followed by logic synthesis. If the circuit under verification is correct, the resulting resynthesized circuit becomes trivially redundant (composed of wires or buffers only). This method outperforms the established SAT-based and equivalence checking techniques and does not require a reference design.

Domaines

Electronique Autre
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Dates et versions

hal-04038793 , version 1 (21-03-2023)

Identifiants

  • HAL Id : hal-04038793 , version 1

Citer

Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej Ciesielski. Formal Verification of Divider Circuits by Hardware Reduction. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2023), Jul 2023, Funchal - Madeira Island, Portugal. paper id 5112. ⟨hal-04038793⟩
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