General introduction Today’s electronic systems are composed of complex Systems on a Chip (SoCs) made of heterogeneous blocks that comprise memories, digital circuits, analog and mixed-signal circuits, etc. To fit a critical application standard requirement, SoCs pass through a comprehensive test flow (functional, structural, parametric, etc.) at the end of the manufacturing process. The goal is to achieve near-zero Defective Parts per Million (DPPM) so as to ensure the quality level required by the standard. Unfortunately, imperfections in the manufacturing process may introduce systematic defects, especially when the first devices are produced while the process is not yet mature. Identification of these systematic defects and correction of the related manufacturing process call for efficient diagnosis techniques. Hence, the goal of diagnosis is to extract information from test data in order to identify the nature and the causes of defects that have occurred in a SoC. Note that additional data can also be produced and used to improve the diagnosis process, such as distinguishing test patterns used only during the diagnosis phase. Failure isolation is critical to identify root-cause of manufacturing issues. The scaling of manufacturing process technology and shrinking of device sizes and interconnects in nano-scale geometries make defect isolation more and more challenging. With the introduction of new transistor devices, lithography, and fabrication technologies, the demand for faster and precise defect isolation will continue to grow. Along with manufacturing process complexity, design complexity has also increased as functionality and computing needs have grown manyfold. Increasing design complexity makes the defect isolation in billon transistor chip ever more challenging. Therefore, fast diagnosis and root-cause identification of failures are essential to maintain high production yields and keep the Moore’s Law in meeting the time to market demand. Chips that pass manufacturing test are then shipped to the customer and integrated in their host system. However, despite the quality level of the manufacturing test procedures, SoCs may fail in the field, either due to the occurrence of a defect not covered during the manufacturing test phase or due to early-life failures or failures caused by various wear-out mechanisms. Early-life failures are caused by latent defects that are not exposed during manufacturing tests, but that are degraded due to electrical and thermal stress during in-field use, and lead to a failure in functionality. Wear-out or aging manifesting as progressive performance degradation, is induced by various mechanisms such as negative-bias temperature instability or hot-carrier injection. To avoid catastrophic consequences, many systems include in-the-field test techniques, which allow the detection of such problems. After detection, the defective SoC must be diagnosed to identify any possible systematic degradation patterns and avoid their re-occurrence in next-generation products. In this context, the first step during the failure identification process is to reproduce the failure mechanism with any original test and test conditions. Next, a diagnosis program made of several routines is used to identify, step by step, the failing part of the defective SoC and, finally, the suspected defects. Each routine corresponds to the application of a diagnosis algorithm at a given hierarchy level (system, core and cell levels). Irrespective of the phase during which a SoC fails (after manufacturing, or after online test if the defective SoC is sent back to the manufacturer), defective SoCs undergo logic diagnosis to locate the fault, and then physical failure analysis (PFA) to characterize the fault. Diagnosis is a software-based method that analyzes the applied tests, the tester responses, and the netlist (possibly with layout information) to produce a list of candidates that represent the possible locations and types of defects (or faults) within the defective circuit. The quality of a diagnosis outcome is usually evaluated owing to two metrics: accuracy and resolution. A diagnosis is accurate if the actual defect is included in the reported list of candidates. Resolution refers to the total number of candidates reported for each actual defect. An accurate diagnosis with perfect resolution (i.e., one) is the ideal case. Diagnosis is usually followed by physical failure analysis (PFA), a time-consuming process for exposing the defect physically in order to characterize the failure mechanism. Due to the high cost and destructive nature of PFA, diagnosis resolution is of critical importance. In practice, it is very uncommon to perform PFA on any defect with more than five candidates. This ensures that the likelihood for uncovering the root-cause of failure is maximized when performing PFA. Historically, conventional approaches based on cause-effect (i.e., fault simulation) and/or effect-cause (i.e., critical path tracing) analysis were used in industry for defect and fault diagnosis. However, with the fast development and vast application of machine learning (ML) in recent years, ML-based techniques have been shown to be highly valuable for diagnosis. They can be used for volume diagnosis after manufacturing to improve production yield or for diagnosis of customer returns to identify any possible systematic degradation patterns. The main advantage of MLbased diagnosis techniques is that they can deal with huge amount of insightful test data that could not be efficiently exploited otherwise in a reasonable amount of time. A wide range of solutions based on supervised, unsupervised and reinforcement learning have been proposed in the last 10 years. They can be used for failure isolation in logic or analog parts of SoCs, board-level fault diagnosis, or even wafer-level failure cluster identification. A plethora of ML algorithms have been experimented and implemented in new diagnosis tools used today in industry. Benefits can be measured in terms of diagnosis accuracy, resolution and duration. This book identifies the key challenges in fault diagnosis of system-on-chip and presents the solutions and corresponding results that have emerged from leadingedge research in this domain. In a comprehensive form, it provides necessary background to the reader and proposes a compendium of solutions existing in this field. The book explains and applies optimized techniques from the machine learning domain to solve the fault diagnosis problem in the realm of electronic system design and manufacturing. It demonstrates techniques based on industrial data and feedback from actual PFA analysis. It also discusses practical problems, including test sequence quality, diagnosis resolution, accuracy, and time cost. The first chapter gives some prerequisites on fault diagnosis. Basic terms, such as defect, fault, and failure, are first enumerated. Then, basic concepts of test and fault simulation are described. After that, the basics of volume diagnosis for yield improvement and fault diagnosis of customer returns are given. Finally, basic information on yield and failure analysis is provided. Chapter 2 is dedicated to the presentation of conventional methods for fault diagnosis. The chapter focuses on the automated tools and methods along with design features at the architectural, logic, circuit, and layout level that are needed to facilitate silicon debug and defect diagnosis of integrated circuits. These design features are generally referred to as design for debug and diagnosis (DFD). The chapter describes how these DFD features along with automated tools and methods are used effectively in a debug or diagnosis environment for applications ranging from design validation, low yield analysis, and all the way to field failure analysis. The chapter can serve as a steppingstone to understand further how conventional methods for fault diagnosis can be improved by using machine learning–based techniques. The third chapter provides details of machine learning techniques proposed so far to solve various VLSI testing problems. It focuses on explaining scope of machine learning in VLSI testing. First, it gives a high-level overview of machine learning. After that, it describes the types of machine learning algorithms. Then, it explains some popular and commonly used machine learning algorithms. After that, this chapter discusses some recent machine learning based solutions proposed to solve VLSI testing problems. Finally, it discusses the strength and limitations of these methods. Chapter 4 is dedicated to machine learning support for logic diagnosis and defect classification. After a preliminary discussion about attempts to distinguish maleficent defects from benign variations, the chapter presents machine learning techniques developed so far for distinguishing variations from reliability threats due to defects. Then, machine learning techniques for identifying different defect types during diagnosis are discussed. A neural network-based fault classifier is presented that can distinguish different fault models at gate level. Finally, the chapter concentrates on distinguishing between transient errors covered by hardening or masking techniques from intermittent faults. A solution based on Bayesian networks is presented for classifying intermittent, transient, and permanent faults. The fifth chapter is dedicated to machine learning in logic circuit diagnosis. It is organized into three main sections that describe the use of ML for pre-diagnosis, during-diagnosis, and post-diagnosis, so as to characterize when and how a given methodology enhances the classic outcomes of diagnosis that include localization, failure behavior identification, and root cause of failure. The first section is dedicated to pre-diagnosis, which is concerned with any activities that are performed before diagnosis is deployed. Examples of pre-diagnosis activities include classic work such as diagnostic ATPG, and DFT for increasing testability. In the second section , the use of ML in during-diagnosis activities is described, which generally involves learning while diagnosis executes. For example, a k-nearest neighbor model can be created, evolved, and used during on-chip diagnosis to improve diagnosis outcomes. In the third and last section, post-diagnosis is discussed, which includes all activities that occur after diagnosis execution. These approaches usually involve volume diagnosis (i.e., using the outcome results of many diagnoses) to improve diagnostic resolution. Chapter 6 gives an overview of the various machine learning approaches and techniques proposed to support cell-aware generation, test, and diagnosis. The chapter focuses on the generation of the cell-aware models and their usage for diagnosis. After some backgrounds on conventional approaches to generate and diagnose cell-aware defects, the chapter will present a learning-based solution to generate cell-aware models. Then, it presents a ML-based cell-aware diagnosis technique. Effectiveness of existing techniques will be shown through industrial case studies and corresponding diagnosis results in terms of accuracy and resolution. The chapter will conclude with a discussion on the future directions in this field. Chapter 7 discusses the state of the art on fault diagnosis for analog circuits with a focus on techniques that leverage machine learning. For a chip that has failed either in post-manufacturing testing or in the field of operation, fault diagnosis is launched to identify the root-cause of failure at subblock level and transistor-level. In this context, machine learning can be used to build a smart system that predicts the fault that has occurred from diagnostic measurements extracted on the chip. The chapter discusses the different elements of a diagnosis flow for analog circuits, including fault modeling, fault simulation, diagnostic measurement extraction and selection, and the machine learning algorithms that compose the prediction system. A machine learning–based diagnosis flow experimented on an industrial case study is finally presented. The eighth chapter discusses machine learning support for board-level functional fault diagnosis. First, the chapter presents an overview of board-level manufacturing tests and conventional fault-diagnosis models. Next, it discusses the motivation of utilizing machine learning techniques and presents the existing machine learningbased diagnosis models. To address the practical issues that arise in real testing data, the chapter next presents a diagnosis system based on online learning algorithms and incremental updates. In the following, it also presents a diagnosis system that utilizes domain-adaption algorithms to transfer the knowledge learned from mature boards to a new board. Chapter 9 is dedicated to wafer-level failure pattern analytics. In the first section of the chapter, the application is about early detection of yield excursions with the goal to automatically recognize the existence of a systematic failure cluster when one occurs. In the second section, analytics is formulated as solving a multiclass classification problem and the discussion focuses on training a high-accuracy neural network classifier. In the next section, techniques to learn an individual recognizer for one pattern class are discussed with the goal to learn with very few training samples. Generative adversarial networks (GANs) and tensor computationbased techniques are used together to implement an unsupervised wafer pattern classification and recognition flow. The last section of the chapter introduces language-driven analytics and explains its use in the analytics context. The authors show how a pretrained language model like GPT-3 can play a role in solving the problem. Finally, a conclusion summarizes the contribution of the book and some perspectives in the field of fault and defect diagnosis of circuits and systems by using machine learning techniques are given.