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Communication Dans Un Congrès Année : 2009

A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems

S. Jovanović
S. Weber
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hal-03938501 , version 1 (13-01-2023)

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S. Jovanović, C. Tanougast, S. Weber. A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems. 2007 2nd NASA/ESA Conference on Adaptive Hardware and Systems, Aug 2007, Edinburgh, United Kingdom. pp.358-364, ⟨10.1109/AHS.2007.4⟩. ⟨hal-03938501⟩
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