Dynamic Voltage and Frequency Scaling (DVFS) involves adjusting the speed to match power consumption and performance requirements of the system. This technology has been shown to provide major power and energy savings in many system components (processor cores, memory system ...). In this work, we study the DVFS mechanism for a processor that implements various levels of speed and power (we call these levels “Pstates”). We model the system as a birth-death process and we compare different configurations, using stochastic comparison, in order to evaluate the impact on the response time and power (and energy) consumption. In the case of two Pstates, we proposed a closed form for the steady state distribution and we derived a cost function that uses both performance and energy consumption. Finally, we derive an algorithm that suggests a threshold which minimizes the cost function.