When deploying Artificial Neural Networks (ANNs) onto multi- core embedded platforms, an intensive evaluation flow is necessary to find implementations that optimize resource usage, timing and power. ANNs require indeed significant amounts of computational and memory resources to execute, while embedded execution plat- forms offer limited resources with strict power budget. Concurrent accesses from processors to shared resources on multi-core plat- forms can lead to bottlenecks with impact on performance and power. Existing approaches show limitations to deliver fast yet accurate evaluation ahead of ANN deployment on the targeted hardware. In this paper, we present a modeling flow for timing and power prediction in early design stage of fully-connected ANNs on multi-core platforms. Our flow offers fast yet accurate predictions with consideration of shared communication resources and scalabil- ity in regards of the number of cores used. The flow is evaluated on real measurements for 42 mappings of 3 fully-connected ANNs exe- cuted on a clock-gated multi-core platform featuring two different communication modes: polling or interrupt-based. Our modeling flow predicts timing with 97 % accuracy and power with 96 % accu- racy on the tested mappings for an average simulation time of 0.23 s for 100 iterations. We then illustrate the application of our approach for efficient design space exploration of ANN implementations.