Nowadays, power optimization has become a major interest for most digital hardware designers. Some, traditionally, might stick to offline power estimation especially in early design phases; some others resort to the modern and very promising runtime power management. Therefore, the Online Power Monitoring (OPM) is considered as an important feature serving real-time power optimization. OPM favors both in-situ power estimation and subsequent prediction, and can be exploited by the Dynamic Voltage and Frequency Scaling (DVFS) mechanism. DVFS, a modern technique for digital circuits power optimization, provides a realtime and adaptive voltage and/or frequency tuning while securing the systems' performance and integrity. In this paper, we present and evaluate an accurate online power monitoring methodology of FPGA IPs. We estimate power consumption using machine learning techniques, based on the IP's most power-influential operating modes and its inputs activity characteristics. The proposed online monitoring mechanism drastically reduces the communication-derived latency between the monitor and the DVFS. Experimental results show a mean absolute percentage error below 1.5% for the estimated power consumption.