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Communication Dans Un Congrès Année : 2022

Analysis of an Inverter-Based CMOS Envelope Detector

Résumé

This article derives the scaling factor of a subthreshold inverter-based envelope detector. The scaling factor was simulated at the transistor-level using BSIM4 model parameters in 180 nm CMOS. A close analysis of the the calculated scaling factor shows that the minimum and the maximum of the scaling factor are within 10 percent of those obtained in simulation, suggesting that the scaling factor of the inverter-based envelope detector biased in the subthreshold region is accurately modeled.
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Dates et versions

hal-03799138 , version 1 (05-10-2022)

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  • HAL Id : hal-03799138 , version 1

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Jack Ou, Pietro Maris Ferreira. Analysis of an Inverter-Based CMOS Envelope Detector. IEEE International Conference on Electronics, Circuits and Systems, Oct 2022, Glasgow, United Kingdom. ⟨hal-03799138⟩
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