Gate-damage safe failure-mode deep analysis under short-circuit operation of 1.2kV and 1.7kV power SiC MOSFET using dedicated gate-source / drain-source voltage depolarization and damage-mode optical imaging - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2022

Gate-damage safe failure-mode deep analysis under short-circuit operation of 1.2kV and 1.7kV power SiC MOSFET using dedicated gate-source / drain-source voltage depolarization and damage-mode optical imaging

Wadia Jouha
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Frédéric Richardeau
Stephane Azzopardi
  • Fonction : Auteur

Résumé

Robustness of 1.2kV and 1.7kV Silicon Carbide MOSFETs submitted to short-circuit operations mode is studied. Experimental results confirm two main failure modes: a safe fail-to-open mode and an unsafe fail-to-short mode. A technique based on direct depolarization of gate source voltage is used to increase the short-circuit withstand capability and to partially obtain a fail-to-open mode. Electro-thermometallurgical simulations are investigated to deeply explain the fail-to-open mechanisms. Finally, using lock-in-thermography and scanning-electronic-microscopy imaging, a new and spectacular lift-off effect of gate-finger is highlighted to clearly confirm the fail-to-open mode capability such devices.
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Dates et versions

hal-03781951 , version 1 (20-09-2022)

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Wadia Jouha, Frédéric Richardeau, Stephane Azzopardi. Gate-damage safe failure-mode deep analysis under short-circuit operation of 1.2kV and 1.7kV power SiC MOSFET using dedicated gate-source / drain-source voltage depolarization and damage-mode optical imaging. IEEE WiPDA-Europe 2022 United Kingdom, Sep 2022, Warwick, United Kingdom. ⟨10.1109/WiPDAEurope55971.2022.9936342⟩. ⟨hal-03781951⟩
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