Low Consumption Balanced Front-end Amplifiers Robust to Load Variations in 65nm PD-SOI CMOS Technology for 60 GHz Shortrange Wireless Applications - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue IEEE Transactions on Circuits and Systems II: Express Briefs Année : 2022

Low Consumption Balanced Front-end Amplifiers Robust to Load Variations in 65nm PD-SOI CMOS Technology for 60 GHz Shortrange Wireless Applications

Résumé

This paper presents two low consumption balanced front-end amplifiers designed in 65nm PD-SOI CMOS technology dedicated to low output power 60 GHz short-range wireless applications. For both designs, a resistive feedback neutralized common source differential pair architecture is used with 90∘ twisted hybrid couplers which allows power combining in addition to an improved robustness against load variations shown by load-pull experimental results. A specific design approach is used to reduce power consumption and limit the output power level. The one-stage amplifier exhibits a gain of 5.43 dB, an OCP1dB of 4.5 dBm, a saturated power superior to 6.33 dBm and a peak PAE of 8.6 % for a total power consumption of solely 14 mW and an active area of 0.17 mm2. The three-stage amplifier exhibits a gain of 21 dB, an OCP1dB of 3.7 dBm, a Psat of 7 dBm and a peak PAE of 8.4 % under a total power consumption of only 42 mW and an active area of 0.3 mm2. All the reported performances are obtained at 60 GHz from a 1V supply voltage.
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Dates et versions

hal-03763357 , version 1 (29-08-2022)

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Citer

Alexandre Berthier, Anthony Ghiotto, Eric Kerherve, Lionel Vogt. Low Consumption Balanced Front-end Amplifiers Robust to Load Variations in 65nm PD-SOI CMOS Technology for 60 GHz Shortrange Wireless Applications. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, pp.1-1. ⟨10.1109/tcsii.2022.3185552⟩. ⟨hal-03763357⟩
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