Communication Dans Un Congrès Année : 2021

Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration

Bruno Ferres
Olivier Muller

Résumé

Hardware design processes often come with timeconsuming iteration loops, as feedbacks generally result of long synthesis runs. It is even more true when multiple different implementations need to be compared to perform Design Space Exploration (DSE). In order to accelerate such flows and increase agility of developers-closing the gap with software development methodologies-we propose to use quick feedback generating transforms based on RTL circuit analysis for quicker convergence of exploration. We also introduce an Hardware Construction Language (HCL) based methodology to build explorable circuit generators, and demonstrate such usage over a General Matrix Multiply (GEMM) Chisel implementation. We demonstrates that using RTL estimation early in the exploration process results in ×7 less synthesis runs and ×4.1 faster convergence than an exhaustive synthesis process, and still achieves state of the art performances when targetting a Xilinx VC709 FPGA.

Fichier principal
Vignette du fichier
article.pdf (354.82 Ko) Télécharger le fichier
Origine Fichiers produits par l'(les) auteur(s)
Licence

Dates et versions

hal-03724027 , version 1 (15-07-2022)

Licence

Identifiants

Citer

Bruno Ferres, Olivier Muller, Frédéric Rousseau. Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration. 2021 IEEE International Workshop on Rapid System Prototyping (RSP), Oct 2021, Paris, France. pp.64-70, ⟨10.1109/RSP53691.2021.9806276⟩. ⟨hal-03724027⟩

Collections

97 Consultations
340 Téléchargements

Altmetric

Partager

  • More