Algorithmic-Level Approximate Tensorial SVM Using High-Level Synthesis on FPGA - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue Electronics Année : 2021

Algorithmic-Level Approximate Tensorial SVM Using High-Level Synthesis on FPGA

Résumé

Approximate Computing Techniques (ACT) are promising solutions towards the achievement of reduced energy, time latency and hardware size for embedded implementations of machine learning algorithms. In this paper, we present the first FPGA implementation of an approximate tensorial Support Vector Machine (SVM) classifier with algorithmic level ACTs using High-Level Synthesis (HLS). A touch modality classification framework was adopted to validate the effectiveness of the proposed implementation. When compared to exact implementation presented in the state-of-the-art, the proposed implementation achieves a reduction in power consumption by up to 49% with a speedup of 3.2×. Moreover, the hardware resources are reduced by 40% while consuming 82% less energy in classifying an input touch with an accuracy loss less than 5%.
Fichier principal
Vignette du fichier
electronics-10-00205-v2.pdf (597.52 Ko) Télécharger le fichier
Origine Fichiers éditeurs autorisés sur une archive ouverte

Dates et versions

hal-03668084 , version 1 (23-05-2024)

Identifiants

Citer

Hamoud Younes, Ali Ibrahim, Mostafa Rizk, Maurizio Valle. Algorithmic-Level Approximate Tensorial SVM Using High-Level Synthesis on FPGA. Electronics, 2021, 10 (2), pp.205. ⟨10.3390/electronics10020205⟩. ⟨hal-03668084⟩
15 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Mastodon Facebook X LinkedIn More