Reliability compact modeling approach for layout dependent effects in advanced CMOS nodes
Résumé
In this paper, we have analysed and modelled the layout dependent effects (LDE) found in pMOSFET transistors from 14nm UTBB FDSOI CMOS technology. Experiments show that changing the layout has a clear impact on threshold Voltage (V th ), under NBTI reliability and on Ring Oscillator (RO) Frequency drift. Compact models taking account the impact of LDE on V th , NBTI reliability, and on RO frequency are proposed. Measurement data are fitted with a new compact model showing that the obtained results are in very good agreements with the modelling.