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Communication Dans Un Congrès Année : 2021

CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks

Résumé

Currently, a major trend in artificial intelligence is to implement neural networks at the edge, within circuits with limited memory capacity. To reach this goal, the in-memory or near-memory implementation of low precision neural networks such as Binarized Neural Networks (BNNs) constitutes an appealing solution. However, the configurability of these approaches is a major challenge: in neural networks, the number of neurons per layer vary tremendously depending on the application, limiting the column-wise or row-wise mapping of neurons in memory arrays. To tackle this issue, we propose, for the first time, a Configurable Analog auto-compensate Pop-Count (CAPC) circuit compatible with column-wise neuron mapping. Our circuit has the advantage of featuring a very natural configurability through analog switch connections. We demonstrate that our solution saves 18% of area compared to non configurable conventional digital solution. Moreover, through extensive Monte-Carlo simulations, we show that the overall error probability remains low, and we highlight, at network level, the resilience of our configurable solution, with very limited accuracy degradation of 0.15% on the MNIST task, and 2.84% on the CIFAR-10 task.
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Dates et versions

hal-03624922 , version 1 (30-03-2022)

Identifiants

Citer

F. Jebali, A. Majumdar, A. Laborieux, T. Hirtzlin, E. Vianello, et al.. CAPC: A Configurable Analog Pop-Count Circuit for Near-Memory Binary Neural Networks. 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug 2021, Lansing, France. pp.158-161, ⟨10.1109/MWSCAS47672.2021.9531919⟩. ⟨hal-03624922⟩
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