Hardware Optimization on FPGA for the Modular Multiplication in the AMNS Representation - Archive ouverte HAL
Chapitre D'ouvrage Année : 2020

Hardware Optimization on FPGA for the Modular Multiplication in the AMNS Representation

Résumé

This paper describes our results of the AMNS modular multiplication algorithm for efficient implementations of ECC over Fp on the Hardware/Software (HW/SW) implementation in FPGA. We provide both arithmetic operators and computation architectures optimized for high speed. We also compare our results with the implementation of the CIOS method for modular multiplication.

Domaines

Arithmétique des ordinateurs Architectures Matérielles [cs.AR]

Fangan Yssouf Dosso  : Connectez-vous pour contacter le contributeur

https://hal.science/hal-03484214

Soumis le : jeudi 16 décembre 2021-22:25:56

Dernière modification le : mardi 27 août 2024-12:53:43

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Dates et versions

hal-03484214 , version 1 (16-12-2021)

Identifiants

Citer

Asma Chaouch, Laurent-Stéphane Didier, Fangan Yssouf Dosso, Nadia El Mrabet, Bouraoui Ouni, et al.. Hardware Optimization on FPGA for the Modular Multiplication in the AMNS Representation. Risks and Security of Internet and Systems, 12026, Springer International Publishing, pp.113-127, 2020, Lecture Notes in Computer Science, ⟨10.1007/978-3-030-41568-6_8⟩. ⟨hal-03484214⟩

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