Modeling of Fermi-level pinning alleviation with MIS contacts: n and pMOSFETs cointegration considerations-Part II - Archive ouverte HAL
Article Dans Une Revue IEEE Transactions on Electron Devices Année : 2016

Modeling of Fermi-level pinning alleviation with MIS contacts: n and pMOSFETs cointegration considerations-Part II

Résumé

In this paper, the insertions of dielectric in metal/insulator/semiconductor contacts are considered via their associated impact on the dc and ac performances. Based on dc output characteristics projections, we found that single insertion and/or single-metal integration schemes are unlikely to result in simultaneously successful Fermi-level pinning alleviation on both n and pFETs. We show that the added C-MIS contributes to a significant extra improvement in terms of intrinsic inverter delay. In particular, an optimal configuration consisting of Pt-liner/p-Si and Zr/TiO$_2$( 15 angstrom)/n-Si contacts can lead to a ring oscillator frequency higher than that of p and nFETs each flanked by ideal ohmic contacts with 10$^{-9}$ Omega.cm$^2$) resistivity.
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Dates et versions

hal-03325006 , version 1 (11-09-2024)

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Julien Borrel, Louis Hutin, Olivier Rozeau, Marie-Anne Jaud, Sebastien Martinie, et al.. Modeling of Fermi-level pinning alleviation with MIS contacts: n and pMOSFETs cointegration considerations-Part II. IEEE Transactions on Electron Devices, 2016, 63 (9), pp.3419-3423. ⟨10.1109/TED.2016.2590826⟩. ⟨hal-03325006⟩
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