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Communication Dans Un Congrès Année : 2021

Effect of gate-source bias voltage and gate-drain leakage current on the short-circuit performance of FTO-type SiC power MOSFETs

Résumé

As a result of short-circuit (SC) stress tests, few commercial 1.2 kV SiC MOSFETs feature fail-to-open (FTO) behavior, that is, a permanent short-circuit between gate and source terminals, even at drain-source bias voltages as high as 600 V. Such devices are very interesting from an application point of view, since such failure mode enables implementation of hoppinghome functionality at a nominal operational voltage and have thus been investigated in depth. This work delivers incremental and complementary understanding on the very timely and highly application-relevant topic of short-circuit withstand capability, aging and failure-mode of SiC power MOSFETs, pointing out new effects and dependence of the degradation state on the bias conditions during test.
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Dates et versions

hal-03288783 , version 1 (16-07-2021)

Identifiants

Citer

Frédéric Richardeau, A. Borghese, A. Castellazzi, A. Irace, V. Chazal, et al.. Effect of gate-source bias voltage and gate-drain leakage current on the short-circuit performance of FTO-type SiC power MOSFETs. 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), May 2021, Nagoya, Japan. pp.255-258, ⟨10.23919/ISPSD50666.2021.9452253⟩. ⟨hal-03288783⟩
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