This paper discusses the design and characterization of a programmable digital delay line. The core of the proposed architecture is a thyristor-type delay element featuring the capability for coarse/fine tuning without using any additional hardware. This is made possible by taking advantage of body biasing features available in 28nm FDSOI CMOS. Body biasing offers unique performance characteristics, notably a very low sensitivity to the biasing voltage. The prototype delay line was designed featuring thermometer-code multi-stage activation and gate/body biasing control. A delay range from 560ps to 16.13ns is exhibited for the delay line with a 2GS/s input stream. The unit delay cell exhibits fs/mV sensitivity combined with an order of magnitude larger delay dynamic range and an energy efficiency of only 12.5 fJ/event.