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Conference Papers Year : 2016

A Digital Delay Line with Coarse/Fine tuning through Gate/Body biasing in 28nm FDSOI

Abstract

This paper discusses the design and characterization of a programmable digital delay line. The core of the proposed architecture is a thyristor-type delay element featuring the capability for coarse/fine tuning without using any additional hardware. This is made possible by taking advantage of body biasing features available in 28nm FDSOI CMOS. Body biasing offers unique performance characteristics, notably a very low sensitivity to the biasing voltage. The prototype delay line was designed featuring thermometer-code multi-stage activation and gate/body biasing control. A delay range from 560ps to 16.13ns is exhibited for the delay line with a 2GS/s input stream. The unit delay cell exhibits fs/mV sensitivity combined with an order of magnitude larger delay dynamic range and an energy efficiency of only 12.5 fJ/event.
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Dates and versions

hal-03270099 , version 1 (24-06-2021)

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Ilias Sourikopoulos, Antoine Frappé, Andreia Cathelin, Laurent Clavier, Andreas Kaiser. A Digital Delay Line with Coarse/Fine tuning through Gate/Body biasing in 28nm FDSOI. 46th European Solid-State Device Research Conference (ESSDERC) / 42nd European Solid-State Circuits Conference (ESSCIRC), Sep 2016, Lausanne, Switzerland. pp.145-148, ⟨10.1109/ESSCIRC.2016.7598263⟩. ⟨hal-03270099⟩
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