Wide-bandgap technology evolution compels the advancement of efficient pulse-widthgate-driver devices. Integrated enhanced gate-driver planar transformers are a source of electromagneticdisturbances due to inter-winding capacitances, which serve as a route to common-mode(CM) currents. This paper will simulate, via ANSYS Q3D Extractor, the unforeseen parasitic effectsof a pulse planar transformer integrated in a SiC MOSFET gate-driver card. Moreover, the pulsetransformer will be ameliorated by adding distinctive shielding layers aiming to suppress CM noiseeffects and endure high dv/dt occurrences intending to validate experimental tests. The correlationbetween stray capacitance and dv/dt immunity results after shielding insertion will be reported.