65 nm SOI CMOS 60 GHz passive mixer for six-port technology - Archive ouverte HAL
Communication Dans Un Congrès Année : 2016

65 nm SOI CMOS 60 GHz passive mixer for six-port technology

Résumé

This work describes the design and measurements of a 60 GHz passive mixer for six-port applications operating and implemented in a 65nm SOI CMOS technology. The mixer topology, consisting only of a n-MOS cold-FET and CPW transmission line matching networks, avoids the use of coupler in front of the detection circuit commonly found in six-port technology. The simplification reduces the chip size and the power consumption. Demodulation results at 60 GHz are demonstrated to validate the approach proposed.
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Dates et versions

hal-03224660 , version 1 (11-05-2021)

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Citer

Kamel Haddadi, Christophe Loyez. 65 nm SOI CMOS 60 GHz passive mixer for six-port technology. IEEE Topical Conference on Wireless Sensors and Sensor Networks, WiSNet 2016, Jan 2016, Austin, TX, United States. pp.52-55, ⟨10.1109/WISNET.2016.7444320⟩. ⟨hal-03224660⟩
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