This work presents the design of an ultra-low-power frequency synthesizer based on a feedback loop composed by an improved version of the Factorial Delay Locked Loop (F-DLL). Its output frequency is controlled by a set of current-starved delay units tuned by a standard DLL feedback loop and a set of logic circuits to generate an RF output frequency proportional to the reference. The objective of this circuit is to achieve a power consumption in the micro-watt range to generate the desired output frequency proportional to the reference frequency between 1.5 and 2.0 GHz, being capable of supporting a wide range of input frequencies with a low phase noise (lower than -90 dBc/Hz at 1 MHz offset) and 370 μW of power consumption. In order to ensure the locking state of the feedback loop and to reduce the phase noise, a modification of the biasing circuit for the voltage controlled delay line (VCDL) is used to improve the linearity of the frequency response of the output using a complementary feedback loop architecture. The circuit was designed and fabricated using the 28 nm FDSOI technology from STMicroelectronics and the measurement results are presented.