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Article Dans Une Revue Electronics Année : 2020

Analysis of the Multi-Steps Package (MSP) for Series-Connected SiC-MOSFETs

Résumé

In this paper, a multi-step packaging (MSP) concept for series-connected SiC-MOSFETs is analyzed. The parasitic capacitance generated by the dielectric isolation of each device in the stack has a significant impact on the dynamic behavior of SiC devices, which impacts the voltage-sharing performances. The study performed in this work reveals that the parasitic capacitance network introduced by the classical planar packaging unbalances the voltage across the series-connected SiC-MOSFETs. Therefore, a new drain-source parasitic capacitance network configuration provided by the MSP is proposed in order to improve the voltage balancing across the series-connected devices. The concept is introduced and analyzed thanks to equivalent models and time domain simulations. To verify the analysis, the voltage sharing between four series-connected 1.2 kV SiC MOSFETs is tested in a double pulse test setup. The experimental results confirm that the MSP has a better performance than the classical one in terms of voltage sharing. Furthermore, the proposed investigation shows that the MSP increases the middle point dv/dt of the switching cell. Sensitive analysis and thermal management considerations are also discussed in order to clarify the MSP limitations and indicate the ways to optimize the MSP from a thermal point of view.
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Dates et versions

hal-03030289 , version 1 (23-12-2020)

Identifiants

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Luciano F S Alves, Pierre Lefranc, Pierre-Olivier Jeannin, Benoit Sarrazin, Jean-Christophe Crebier. Analysis of the Multi-Steps Package (MSP) for Series-Connected SiC-MOSFETs. Electronics, 2020, 9 (9), pp.1341. ⟨10.3390/electronics9091341⟩. ⟨hal-03030289⟩
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