Variant Calling Parallelization on Processor-in-Memory Architecture - Archive ouverte HAL
Communication Dans Un Congrès Année : 2020

Variant Calling Parallelization on Processor-in-Memory Architecture

Remy Cimadomo
  • Fonction : Auteur
  • PersonId : 1081628
Romaric Jodin
  • Fonction : Auteur
  • PersonId : 1081629

Résumé

This paper introduces a new combination of software and hardware PIM (Process-in-Memory) architecture to accelerate the variant calling genomic process. PIM translates into bringing data intensive calculations directly where the data is: within the DRAM, enhanced with thousands of processing units. The energy consumption, in large part due to data movement, is significantly lowered at a marginal additional hardware cost. Such design allows an unprecedented level of parallelism to process billions of short reads. Experiments on real PIM devices developed by the UPMEM company show significant speed-up compared to pure software implementation. The PIM solution also compared nicely to FPGA or GPU based acceleration bringing similar to twice the processing speed but most importantly being 5 to 8 times cheaper to deploy with up to 6 times less power consumption.
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Dates et versions

hal-03006764 , version 1 (16-11-2020)

Identifiants

  • HAL Id : hal-03006764 , version 1

Citer

Dominique Lavenier, Remy Cimadomo, Romaric Jodin. Variant Calling Parallelization on Processor-in-Memory Architecture. BIBM 2020 - IEEE International Conference on Bioinformatics and Biomedicine, Dec 2020, Virtual, South Korea. pp.1-4. ⟨hal-03006764⟩
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