This paper describes a BIST technique for the static linearity test of $V_{cm}$ -based successive-approximation analog-to-digital converters (SAR ADCs). We discuss the application of reduced-code techniques for the $V_{cm}$ -based SAR ADC topology and present a practical on-chip implementation based on an embedded incremental ADC. Simulation results are provided for validating the feasibility and performance of the proposed on-chip reduced-code static linearity test.